MPX 100 Theory of Operation - Service Manual Version

SCHEMATIC WALK-THROUGH

Sheet 1: 
This sheet shows the analog input section (U20-22), ADC (U17), DAC (U13), analog output section (U16, 18 & 19) and their associated circuitry, as well as the output mute circuit (U18).


Input Stage 
Separate unbalanced 1/4" unbalanced phone jacks (J8 and J9) are provided for left and right input signals. A single input source will be routed to both left and right input stages if only the right input (J9) is used. J8 and J9 also provide chassis ground through an integrated ground lug from the PCB to the cover. 

Capacitors (C75 and C86) are found at the inputs to prevent unwanted high frequency interference from entering or leaving MPX 100 through the input cables.

DC blocking is incorporated by capacitors (C74 and C85) in line with the signal path. 

The input impedance of the MPX 100 is set by R110 and R124, 1M Ohm per channel and 500K Ohm when sum-to-mono by plugging in the Right I/P only. This allows the MPX 100 to be used with a wide variety of input sources including electric guitars. Because of the high input impedance, the input is very susceptible to noise pickup from radiating sources. This is not a problem with an instrument plugged in as the instruments relatively low (1k-10k) output impedance provides a path to ground. 

However, when the plug is empty, there is a full 1Meg for a noise voltage to form across. For this reason the left and right inputs short to ground when empty. 

D24 and D25 protect U20 and U22 from being destroyed by large input signals. R111 and R123 limit the current through D24 and D25 during conduction to protect them. This insures signals at the input of the U20 and U22 are never greater than 0.7V above the op-amp rails. 

The non-inverting inputs of one half U20 and U22 are used as the signal input buffer to maintain a high input impedance, provide unity gain at low frequencies, as well provide pre-emphasis. 

R112, R113, C78 and R121, R122, C91 are feedback networks around U20 and U22 respectively. They form a high pass shelf for pre-emphasis. It is a 10 dB shelf starting at 3 kHz and ending at 9 kHz. This is 15/50uS curve with matching de-emphasis on the output. The pre/de-emphasis improves the SNR of the unit. Capacitors C79, C92 provide high frequency compensation for this input buffer stage. 

C96 and C97 remove offset so potentiometer wiper noise in R116 is eliminated. R116 is a ganged dual pot for input level control. 

The second half of U20 and U22 is a gain stage which provides approximately 25db of gain. R114, R115 and R125, R126 set the gain of the respective channels. C82 and C95 are used for op-amp compensation at high frequencies. C80, C81, and C93, C94 are power supply bypass capacitors for U20 and U22.

U21 provides a unity gain inverting stage. This in conjunction with the output of the prior gain stage provide the differential input to the CS5335 A/D converter (U17). R117, R118 and R119, R120 set the gain to unity. C87 and C90 provide high frequency compensation for this inverting stage. C88 and C89 are power supply bypass capacitors for U21.

Capacitors C76, C83 and C77, C84 block the 2.5VDC level shift generated by the self-biasing of the CS5335 A/D (U17) inputs. The combined output of the inverting stage and the non-inverting gain stage provide 6db more gain at the differential inputs of the A/D. This guarantees full scale input to the A/D converter with a low level input signal.

Last R106, R107, C70 and R109, R108, C71 provide anti-aliasing filter before the 
conversion. The corner frequency of this filter is 240kHz.

R99, C63, C65 and C62, C64 filter the analog 5V supply for the ADC.


A/D
The Crystal CS5335 (U17, schematic page 1) is a complete stereo analog-to-digital converter which performs anti-alias filtering, sampling, A/D conversion generating 24 bit values for both left and right inputs in serial form. The CS5335 operates in slave mode where SCLK and LRCLK are inputs. 

Data is clocked in on the rising edge of the bit clock (64FS) and is aligned with the second bit clock following the leading edge of each transition in the LRCLK (FS). This alignment is determined by setting the serial data interface format pins on the CS5335 to support the I2S format. 

The Lexichip 3 Serial Receive port (SDIN0) will need its mode and configuration registers set to accommodate I2S format data. 

Upon power-up, the digital filters and delta-sigma modulators are reset, and the internal voltage reference is powered down. The device will remain in the power down mode until MCLK (256FS, 11.2896 MHz) and LRCLK (FS, 44.1 kHz) are presented. Once MCLK and LRCLK are detected, MCLK occurrences are counted over one LRCLK period to determine the MCLK/LRCLK frequency ratio. Then the internal voltage reference is determined and power is applied and the analog inputs will move to approximately 2.2V.

The initialization and settling sequence requires approximately 28672 periods of LRCLK (650mS at a 44.1 kHz sample rate). This time is dominated by the settling time required for the integral high pass filter which is enabled to remove DC offset within the A/D converter. 

D/A
The Crystal CS4327 (U13, schematic page 1) is a Delta-Sigma architecture digital-to-analog converter. The CS4327 can be configured to operate in a variety of modes. In MPX 100 the Digital Input Format is set to support the I2S serial protocol. 

The DAC is set run from a 256FS MC, same MC as the A/D, this is generated by the Lexichip 3. Data is clocked in on the rising edge of the bit clock (64FS) and is aligned with the second bit clock following the leading edge of each transition in the LRCLK (FS). This alignment is determined by programming the Lexichip 3 Serial Transmit port (SDOUT0) to support the I2S format.

Output Stage
R86, C39, C40, C41, C42 filter the supplies to the CS4327 DAC (U13).

Coming out of the DAC are Capacitors C48, C49 which remove a 2.2V offset from the DAC. R90 and R94 give U16 inputs a bias current path and references the signal from the DAC to ground.

U16 and its associated components R93, R95 C52, C55 and R89, R91, C50, C54 form a second order unity gain low pass filter of Sallen-Key type. R96, C58 and R92, C57 form first order low pass filter. The two filters sets combined form a third order anti-imaging filter at 100kHz. C51 and C56 are power supply bypass capacitors for U16.

C53 and C59 are DC blockers which eliminate any offset from U16 to prevent potentiometer wiper noise in R97. R97 is a ganged dual pot for output level control. 

Two analog switches (U18) provide output muting during power up and power down conditions. The MUTE/ signal which controls these switches is generated from the
a control register which is set low on power reset. This signal is terminated at pins 9 and 10 of U18. When MUTE/ is low, pins 4 and 5 of U18 are connected for the right output and pins 15 and 2 of U18 are connected for the left output, creating a low impedance signal path to ground. These switches are place in parallel with the output level potentiometer before the output stage. Approximately 43db of attenuation is achieved when the switch is on (MUTE/ is low). 

A dual op amp (U19) and its associated circuitry (R101, R102, C68 and R103, R104, C69) make up the final output stage. This stage provides 10.5db of gain and the complimentary de-emphasis curve to compensate for the pre-emphasis function performed before the conversion process. C67 and C73 are the +V and -V power supply bypass capacitors for U19.

An impedance of 75 Ohms is developed by R88 and R98 for the left and right outputs respectively . These resistors also provide current limiting protection. The output 1/4" unbalanced phone jacks (J6 and J7) are configured in such a way that, when only the right jack (J7) is connected, the left and right outputs are summed together to provide a mono output. The left jack (J6) can support stereo headphones if the right jack is not connected. The left channel appears on the tip and the right channel appears on the ring of a stereo phone plug of this three conductor 1/4" phone jack. C47 and C61 are provided for RFI suppression at the outputs.

Although the output op amp can drive high-impedance (>100 Ohms) headphones, it is not designed for low impedance headphones. For best results, use a headphone amp. 


Sheet 2: 
The heart and soul of MPX 100 is found on this page.

This sheet shows the Z80 (U8), ROM (U10), SRAM (U9), Lexichip 3 (U5) and its audio memory (U3), as well as a EEPROM (U2) for non-volatile storage. The pull up/down resistors on the system data bus are used to program the Lexichip 3 operating mode. Upon the rising edge of RESET/ various Lexichip 3 mode bits are set which determine system operating parameters. This is done externally by pull-up/down resistors R59-R66. This is possible because no one else is driving the bus during reset. The 10MHz Z80 (U8) can run at 5.6448 MHz or 9.0316Mhz depending on how the resistors are programmed on the data bus. 

EPROM location (U10) can support 64k (27C512) or 128k (27C010,70ns).

Running the Z80 at 9.0316MHz and using the zero wait states for ROM access we can accommodate a ROM with an access time of 112nS or better. By inserting one wait state we can use a ROM with an access time of 223nS or better. 

8K x 8 SRAM (U9) can have a relatively slow access time, 80ns, and faster will operate with one waitstate with the Z80 running at 9 mHz. 

Clocks
This chip mode determines various system parameters: Host address decode map, masterclock frequency and source, and zclock frequency and source. Given the desire to have an audio sample rate of 44.1KHz, the Lexichip 3 crystal input is selected as 11.2896 MHz, the internal PLL bumps this up 4X to a Lexichip 3 master clock frequency of 45.1584 MHz. All other clocks, including ZCLK/ are derived from this Lexichip 3 master clock. The conversion clocks, FS, 64FS, and 256FS are derived from the 11.2896 MHz xtal.


Audio Memory
Even though an internal data path width of 24 bits is supported, a smaller multiplexed external DRAM data path is used to reduce external parts count, and provide cost effectiveness. MPX 100 is currently set-up to have its DRAM data path initialized to 4 bits wide. This is done by setting the appropriate fields in the Lexichip 3 Sub Mode Control Register 1.

The audio memory compliment is a single 60ns, 4Mbit DRAM (1M x 4), U3. Four 4 bit accesses are assembled for a sixteen bit word. DRAM address and control lines have the option of using series dampening resistors. These are represented by R18-R30.

EEPROM
Non-volatile  data storage is incorporated with a 2 wire serial/I2C 24C04 (4K bit) EEPROM similar to the device used in Reflex. 

This serial EEPROM (U2) uses a two wire bus protocol. U2, pin 5 is the serial address/data input/output, this is a bi-directional pin used to transfer addresses and data into and out of the device. U2, pin 6 is the serial clock input used to synchronize the data transfer to and from the device. 

Currently pins 98 and 96 of Lexichip 3 are configured as PIOB(7) and PIOB(4).  PIOB(7)(pin 96) is used to generate the serial clock and PIOB(4)(pin 98) is the bi-directional address/data for the EEPROM. 

EEPROM_DATA is pulled high through R17, this signal must remain in a high logic state, this is so the EEPROM SDA signal can pull this signal to a low logic level to generate an acknowledge pulse after the reception of each byte.

Sheet 3:
Sheet 3 includes the front panel Encoders and Pot A/D.

Encoders
It is necessary to have pull-up resistors at the Front Panel encoders (SW3 and SW4). R48 - R51 pulls up the inputs, this prevents Lexichip 3 inputs from floating and provides a default non-active switch state of logic high. Diodes D13-D16 (PROGRAM Encoder) and D18-D21 (VARIATION Encoder) are used to isolate the output of the unselected encoder during the reading of the selected encoder. An Encoder is selected when its C pin is set low, allowing the corresponding group of diodes to conduct and indicate the gray-scale code for the selected encoder's current position. A NAND gate (U7) is used as an inverter to guaranty exclusive
selection of the active encoder. 

Control Input (IAD)
The pot A/D converter is the integrating type made from current source Q5 and 8bit timer in the Lexichip 3. To start the conversion, the Z80 tells the Lexichip 3 to bring RESET_IAD high, which toggles U23 and discharges capacitor C38 to less than 0.2V. Next the Z80 selects which pot (ADMUXIN0 - 3) the Lexichip 3 will digitize. It does this by writing to a IAD mux register in the Lexichip 3. 

The Lexichip 3 then starts its timer and brings RESET_IAD low. C38 starts to charge from the current source. Once the capacitor voltage exceeds the pot voltage, the muxed comparator output goes low. This produces a high level interrupt to the Z80, which disables the timer. At its convenience the Z80 reads the timer and derives the voltage on the pot. R80 sets input voltage range from 0-3V. This voltage is also the calibration voltage for the IAD, it will guaranty the pots full range will be used regardless of fluctuation in voltage and temperature. 

Sheet 4:
Sheet 4 includes the external footswitch inputs, front panel LED/Switch matrix, and control register (U11).

Footswitch 
Footswitch jack J2  use resistors (R10, R12) and capacitors (C8, C9) to filter out RFI. D10 and D11 help protect from over voltage or static shock and R11 and R13 provide a default non-active switch state of logic high.


LED/Switch Matrix
There are eight discrete LED's on the front panel, which are organized into 2 columns and 4 rows. 

An octal D-Flop U11 clocks the data bus on the rising edge of CTL_REG/. Bits 4 (COLUMN_STRB0) and 5 (COLUMN_STRB1) are active low column select lines. These are buffered and inverted by switching transistors Q3 and Q4. When a selected COLUMN line is driven high and ROW line is driven low, the LED at the cross point of the column and row will light. Also if the one of the front panel switches in the selected column is pressed, the SWITCH_ROW signal corresponding to its row will go high. R6 and R8 pull non-selected columns to ground, which is necessary for the proper detection of the switches.

We also drive the row lines directly from U11. We can get away with this because U11 is only driving four lines, so the total current in the IC remains well below 100 mA. The 100-Ohm resistors (R70-R73) limit the row current to about 28 mA or less. 

Sheet 5:
Sheet 5 includes the power supply & master reset circuitry, the Midi I/O, S/PDIF output, and Z80 reset.

Power Fail/Reset
Reset signaling is controlled by the +5UNREG voltage. If the +5UNREG voltage at the input of the +5VD regulator (U1) is high enough to create a 2 volt or greater drop across the regulator then the differential between the voltage divider (R2 and R3 at the emitter of Q2, and the regulated +5VD at the base of Q2 will be enough to turn on Q2. As Q2 turns on, it charges C7 through R4. The voltage across R5 and R4 goes from 0V to about +6V. R4 is also used as a voltage divider to generate RESET/ at a 5V level taking Lexichip 3, CS5335 A/D, and the CNT_REG/ out of reset. C7 is discharged through D5 on power down. 

The MPX 100 power supply provides three regulated DC output voltages: +5VD for digital circuits, +5VA and -5VA for analog circuits.
AC power is provided by an external transformer rated at 9VAC @ 1.9A. The transformer output is terminated with a 5 mm/2.5 mm barrel type connector (J1), with its mating input jack located at the rear panel of MPX 100. A .1 uF capacitor, C1 is connected across the AC input to help prevent noise spikes from entering the unit. In addition C1 and C2 (470pf) stop circuit generated RFI from radiating through the power line.

All three regulated supplies (+5VDC analog, -5VDC analog and +5VDC digital) consist of a single diode (D1, D2 and D3) used as a half wave rectifier to produce the unregulated 5 volt supply (approximately 10 VDC) across each supply's filter capacitor (C3, C4, and C5). The analog supplies use 1000 uF electrolytics and the digital supply uses a 3300 uF electrolytic capacitor due to the added load of more circuitry and front panel LED's. Digital supply is post-regulator filtered with a 22 uF capacitor (C6) and analog circuit supplies use a 4.7uF, capacitor (C46) and a 22uF capacitor (C45). The +5VUNREG supply is monitored by the reset circuit for power up and power fail conditions.

Voltage regulation is handled by three TO-220 packaged ICs: 

	+5VD digital circuits - U1 (LM2490)
	+5VA analog circuits  - U14 (LM2490)
	-5VA analog circuits  - U15 (MC7905)

Current limiting and short circuit protection are incorporated into the internal circuitry of these ICs.

The MPX 100 power supply also provides two unregulated DC output voltages: +V and -V for the analog output stage at U19. The +V and -V power supplies were added to help isolate the output stage from the rest of the power supply, and to delay the turn-on during power up to minimize the power on thump characteristics at the analog output. 

The unregulated +V supply (C99, C100, R132, R133 & Q6) and -V supply (C101, C102, R134, R135 & Q7) are both derived from capacitance multipliers which multiplies the value of the capacitor by the beta of the transistor for a higher (but poorly regulated) output voltage.

Fifteen +5VD bypass caps are represented on page 5 of the schematic. 

MIDI I/O
The MIDI interface utilized by MPX 100 complies with the MIDI specification. It incorporates 5 pin, female DIN connectors for input and output (J4 and J3). MIDI IN is opto-coupled for ground isolation through U4 to the UART (in Lexichip 3). The MIDI OUT signal is provided by Lexichip 3 and is fed to current loop driver Q1 and out J3. FB1 and FB2 are used to reduce RFI radiation.

S/PDIF Out
The S/PDIF output signal is generated using a pair of 74HC132's. Each gate has to source about 6.25 mA, well within its capabilities. The resistors are selected so that the voltage across R52 is 0.5Vpp, assuming 75 Ohm load resistor across the S/PDIF connector and a Voh out of the gates of 4.7V, which typical Voh at 6mA.

C28 and C30 were added to the circuit to help meet RF compliance. However, they also band-limit the S/PDIF signal, which increases jitter. D17 helps protect from over voltage or static shock.

Z80 RESET
In order to guaranty the data bus is tri-stated when the Lexichip 3 is released from reset, the Z80 must have a clock present at its ZCLK input when the Z80 released from reset. This is accomplished by using a 74HC132 (U7), along with C32 (10pf) and R55 (47k) as a feedback oscillator. A 74HC157 (U6) is used  to select the ZCLK source from either the U7 oscillator or the Lexichip 3, and also gates the reset signal for the Z80 during reset.

During power up while RESET/ is asserted low, the feedback oscillator is enabled by bringing U7 pin 1 high. The oscillators output is selected as the ZCLK, and ZRST is held low by U6.

When the RESET/ signal goes high, the feedback oscillator is disabled as U7 pin 1 is brought low, the ZCLK_LEXI3 clock (from the Lexichip 3) signal is selected as the ZCLK, and ZRST is controlled by ZRST_LEXI3 signal (from the Lexichip 3).

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